Device Family: Intel® Cyclone®, Cyclone® IV, Cyclone® IV GX

Type: Answers

Area: Component, HSIO



Why do I see bit errors on Rx channel 0 of transceiver block GXBL1 when I de-assert the gxb_powerdown signal of transceiver block GXBL0 when using Cyclone IV GX EP4CGX150 and EP4CGX75 devices?

Description

You may see bit errors on Rx channel 0 of transceiver block GXBL1 when you de-assert the gxb_powerdown signal of transceiver block GXBL0 when using Cyclone® IV GX EP4CGX150 and EP4CGX75 devices due to coupling inside the device.

Designs that may be affected are:

  • Cyclone IV GX EP4CGX150 and EP4CGX75 devices that use transceiver banks GXBL0 and GXBL1 AND
  • Rx channel 0 in transceiver bank GXBL1 is used AND
  • Tx Channel 3 in transceiver bank GXBL0 is used AND
  • The gxb_powerdown signals of transceiver banks GXBL0 and GXBL1 are controlled independently.

Affected designs may need to be resynchronized.

Workaround/Fix

To work around this problem, do not use the gxb_powerdown signal for transceiver bank GXBL0. Instead you can assert the pll_areset, tx_digitalreset, rx_analogreset, and rx_digitalreset signals.