Device Family: Cyclone® V E

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why is my DDR3 hard memory controller ODT not toggling?

Description

There is a problem with the DDR3 hard memory controller that causes the ODT signal (mem_odt) to remain high during write and read accesses.

Workaround/Fix

The workaround is as follows:

  1. In the MegaWizard Memory Parameters tab, set MR1 RttNom to disabled, set MR2 RttWr to RZQ/4 (or whatever value works best for your board)
  2. Regenerate the IP
  3. Make the following change to force the mem_odt signal permanently high. Open the *_p0_*_addr_cmd_pads.v file and change the datain connection in the ucmd_pad instantiation as follows:

From :

.datain({ phy_ddio_we_n, phy_ddio_cas_n, phy_ddio_ras_n, phy_ddio_odt, phy_ddio_cke,  phy_ddio_cs_n})
 
To:

.datain({ phy_ddio_we_n, phy_ddio_cas_n, phy_ddio_ras_n, 4\'b1111, phy_ddio_cke, phy_ddio_cs_n})

Recompile the design and observe with a scope that mem_odt is always high. By disabling RttNom and enabling RttWr, it ensures that ODT in the memory device is only turned on for write accesses.

This issue will be fixed in a future release of the Quartus® II software.