Device Family: Stratix® V GX

Type: Answers

Area: Component

Area: EMIF


IP Product: RLDRAM II Controller with UniPHY

Why do I see fitter or Timequest warnings about missing or ignored clocks when using UniPHY based external memory Interface IP in a Qsys project?

Description

In the Qsys project .qip file, the UniPHY external memory interface IP sdc files may not be in the correct order and this can be a reason for missing or ignored clock warnings or critical warnings. This is typically seen when the UniPHY IP is used with PLL and DLL sharing between two interfaces.

Workaround/Fix

Two possible workarounds are :-

1)     Comment out the sdc files in the Qsys .qip file and add them in the required order in the Quartus Project Settings -> Timequest Timing Analyzer  -> SDC files to include in the project

 

2)     Modify the Qsys .qip file to put the sdc files in the required order.

For each UniPHY IP instance, place the <UniPHY_IP_variation_name>_p0.sdc file before the other sdc files for that UniPHY IP.

For the clock sharing timing flow to work correctly, the .qip file order (and hence timing sdc files) must be such that the master sdc files are listed before any associated slave sdc files.

For further information, see the “The DLL and PLL Sharing Interface” section in the Functional Description – UniPHY chapter in volume 3 of the External Memory Interface Handbook.

This issue is planned to be fixed in a future version of the Quartus® II software.