When bonding two DDR3 hard memory controllers in Cyclone® V or Arria® V, you may experience timing violations on the bonding interface. These violations are valid.
Device Family: Arria® V GT, Arria® V GX, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX
Area: Component, EMIF
The workaround is to insert pipeline registers for the bonding signals.