Device Family: Arria® V GT, Arria® V GX, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: Component, EMIF

Are the timing violations on the bonding interface of my Cyclone V or Arria V DDR3 bonded hard memory controller design valid?


When bonding two DDR3 hard memory controllers in Cyclone® V or Arria® V, you may experience timing violations on the bonding interface. These violations are valid.


The workaround is to insert pipeline registers for the bonding signals.