Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Arria® II GX, Arria® II GZ, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® III, Cyclone® III LS, Cyclone® IV E, Cyclone® IV GX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® II, Stratix® II GX, Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Intellectual Property


IP Product: Triple Speed Ethernet with 1588 MegaCore

Why does Triple Speed Ethernet IP Core pad two octet zeros ahead of MAC destination address?

Description

To align packet headers to a 32-bit boundary, Triple Speed Ethernet IP Core pads two octet zeros ahead of the MAC destination address if 'Align packet headers to 32-bit boundary' option is enabled.