Device Family: Arria® II GX, Arria® II GZ, Arria® GX, Cyclone® IV GX, Stratix® II GX, Stratix® IV GT, Stratix® IV GX

Type: Answers

Area: Component, HSIO



What is the reset sequence for high speed GX transceivers in loss of link conditions in Altera GX/GT/GZ device families?

Description

Device handbooks provide reset sequences for high speed transceiver initialization during link bring up. This solution addresses the reset sequence in loss of link conditions. 

Loss of link can occur due to loss of local reference clock source or loss of the link due to an unplugged cable. Other adverse conditions like loss of power could also cause the loss of signal from the other device/link partner.

Loss of local REFCLK (or other reference clock) condition:

Should local reference clock input become disabled or unstable, take the following steps.

  • Monitor pll_locked signal.  Pll_locked will de-assert if local reference clock source becomes unavailable. 
  • Pll_locked assertion indicates a stable reference clock, as TX PLL locks to the incoming clock.  You can follow appropriate reset sequence provided in the device handbook, starting from pll_locked assertion.

Loss of link due to unplugged cable or far end shut-off condition:

Use one or more of the following methods to identify if link partner is alive or not.

1. Signal detect is available in PCIe and Basic modes.  You can monitor rx_signaldetect signal as loss of link indicator. rx_signaldetect will assert, as the link partner comes back up.

2. You can implement a PPM detector in device core for modes that do not have signal detect to monitor the link. PPM detector will help you identify if link is alive or not.

3. Data corruption or RX phase comp fifo overflow/underflow condition in user logic may indicate a loss of link condition.

One of the following reset sequences should be applied after loss of link detection from methods described above.

1. For Automatic CDR lock mode:

  • Monitor rx_freqlocked signal.  Loss of link will cause rx_freqlocked to de-assert, when CDR moves back to Lock-to-Data (LTD) mode.
  • Assert rx_digitalreset.
  • You may see rx_freqlocked toggling over time, as CDR switches between Lock-to-Reference (LTR) and Lock-to-Data (LTD) modes.
  • De-assert rx_digitalreset, after rx_freqlocked is high for an amount of time equal to tLTD_Auto (see device Datasheet).

Note: This step does not apply to Cyclone®  IV GX devices, due to functional differences.  rx_freqlocked should not be used as CDR Lock-to-Data (LTD) indicator.  For Cyclone IV GX devices, a PPM detector must be implemented in user logic to determine the presence of link and a stable recovered clock, before de-asserting the rx_digitalreset.

  • If rx_freqlocked goes low at any point, re-assert rx_digitalreset.
  • If data corruption or RX phase comp fifo overflow/underflow condition is observed in user logic, assert rx_digitalreset for 2 parallel clock cycles, then de-assert.

This solution may violate some of the protocol specific requirements.  In such case, you could use Manual CDR lock option. 

2. For Manual CDR lock mode, rx_freqlocked signal is not available. Upon detection of a dead link, take the following steps:

  • Switch to the lock-to-reference (LTR) mode
  • Assert rx_digitalreset.
  • Wait for rx_pll_locked to go high
  • When you detect incoming data on the receive pins (as described earlier), switch to lock-to-data (LTD) mode. 
  • Wait for tLTD_Manual duration (see device Datasheet). 
  • De-assert rx_digitalreset.