Type: Answers

Area: Tools



Error: Clock input port inclk[<number>] of PLL "<name>" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block

Description

You may see this error if you assign a PLL as a black box for the formal verification flow in the Quartus® II software. This error can occur when the black box has been assigned to a level of PLL hierarchy which has constants driving one or more clock inputs. To avoid this error, assign the black box to a level of PLL hierarchy without constant clock inputs.

For example, if one of the PLL clock inputs is unused and this input tied to a constant value, this error may occur if the black box is assigned to a level of hierarchy with the following command:

set_instance_assignment -name EDA_FV_HIERARCHY BLACKBOX -to \
"my_pll:my_pll_inst|altpll:altpll_component"

Because the constant values on the unused inputs do not propagate to the next higher level, you can avoid this error by assigning the black box to the next level up in hierarchy with the following command:

set_instance_assignment -name EDA_FV_HIERARCHY BLACKBOX -to "my_pll:my_pll_inst"