Device Family: Stratix® IV GT, Stratix® IV GX
Type: Answers
Area: Intellectual Property


Last Modified: January 06, 2016
Version Found: v13.0 Service Pack 1
IP Product: PCI Express 1/2/4/8 Lanes (x8)

Error: pcie_hard_ip_0_pcie_bfm_0: altera_pcie_bfm_qsys does not support generation for VHDL Simulation. Generation is available for: Verilog Simulation, Quartus Synthesis

Description

You may encounter this error when you attempt to generate a VHDL testbench for the Stratix® IV IP Compiler for PCI Express® under Qsys.

Workaround/Fix

To avoid this error, use Verilog HDL for the testbench. The VHDL testbench is not available for Stratix IV designs.

This problem is not scheduled to be fixed.

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