You may encounter this error when you attempt to generate a VHDL testbench for the Stratix® IV IP Compiler for PCI Express® under Qsys.
Last Modified: January 06, 2016
Version Found: v13.0 Service Pack 1
IP Product: PCI Express 1/2/4/8 Lanes (x8)
To avoid this error, use Verilog HDL for the testbench. The VHDL testbench is not available for Stratix IV designs.
This problem is not scheduled to be fixed.