Device Family: Intel® Arria® 10 GT

Device Family: Intel® Arria® 10 GX

Device Family: Intel® Arria® 10 SX

Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: Intellectual Property


IP Product: PCI Express Gen 3,2 or 1 x8,4,2,1 Hardened IP

Why do I see dropped Read or Write requests when simulating the Hard IP for PCI Express Avalon-MM DMA core?

Description

Due to a problem with the testbench generated by IP Catalog or Qsys®, you will see dropped transactions if your test issues closely spaced (back to back) memory reads or writes from the Endpoint (to the Rootport).  This applies to the Avalon®-MM with DMA variants.

Workaround/Fix

To work around this problem, increase the time between your upstream requests.

Altera® recommends using a third-party commercial Root Port Bus Functional Model (BFM) for production verification of the Altera PCIe Hard IP.

This problem is not scheduled to be fixed in a future Quartus® Prime software release.