Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Intellectual Property

IP Product: PCI Express 1/2/4/8 Lanes (x8)

Why does the Arria 10 Hard IP for PCI Express CraWaitRequest_o never deassert for CRA internal configuration space registers?


Due to a problem in the Arria® 10 Hard IP for PCI Express® in Avalon®-MM mode, the Control Register Access(CRA) waitrequest signal (CraWaitRequest_o) never deasserts for accesses to the CRA configuration space registers (offsets 0x3c00 - 0x3c6c).


Modify the following always block starting at ~ line 340 in the file altpciexpav128_cr_avalon.v to add the item in bold to the sensitivity list:

   // Select the returned read data and read valid
   always @(addr_decode_reg or AdTrReadData_i or AdTrReadDataVld_i or
            A2PMbReadData_i or A2PMbReadDataVld_i or
            P2AMbReadData_i or P2AMbReadDataVld_i or
            RuptReadData_i or  RuptReadDataVld_i or
            RpReadData_i   or  RpReadDataVld_i or
            RdBakReadData_i or RdBakReadDataVld_i or CfgReadDataVld_i)

This problem is scheduled to be fixed in a future release of the Quartus® II software.