Article ID: 000080203 Content Type: Troubleshooting Last Reviewed: 07/30/2015

Why does the Arria 10 Hard IP for PCI Express CraWaitRequest_o never deassert for CRA internal configuration space registers?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to a problem in the Arria® 10 Hard IP for PCI Express® in Avalon®-MM mode, the Control Register Access(CRA) waitrequest signal (CraWaitRequest_o) never deasserts for accesses to the CRA configuration space registers (offsets 0x3c00 - 0x3c6c).
    Resolution

    Modify the following always block starting at ~ line 340 in the file altpciexpav128_cr_avalon.v to add the item in bold to the sensitivity list:

       // Select the returned read data and read valid
       always @(addr_decode_reg or AdTrReadData_i or AdTrReadDataVld_i or
                A2PMbReadData_i or A2PMbReadDataVld_i or
                P2AMbReadData_i or P2AMbReadDataVld_i or
                RuptReadData_i or  RuptReadDataVld_i or
                RpReadData_i   or  RpReadDataVld_i or
                RdBakReadData_i or RdBakReadDataVld_i or CfgReadDataVld_i)

    This problem is scheduled to be fixed in a future release of the Quartus® II software.

    Related Products

    This article applies to 16 products

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