Device Family: Stratix® III

Type: Answers

Area: EMIF


Last Modified: December 11, 2018
IP: DDR3 SDRAM Controller with UniPHY

Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.

Description

You may see the critical warning above during the fitter stage when compiling the UniPHY-based memory controller IP. 

Workaround/Fix

You may safely ignore this critical warning message.