Device Family: Stratix® V, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why is ‘Report DDR’ timing report missing when I have multiple instances of a wide external memory interface?

Description

Due to an issue in a timing script for the Quartus® II software version 12.1SP2 and earlier, a design with multiple instances of wide (typically x72 bits or more) external memory interfaces might not show the ‘Report DDR’ timing report. If the "Report DDR" timing report is shown then this issue does not affect your design.

 

Workaround/Fix

Identify and open the <project_name>_p0_report_timing_core.tcl, and look for the line with key word ‘num_path’. Make following change in that line.

 

From:

set num_paths 5000

 

To:

set num_paths 10000

 

This issue will be fixed in a future release of the Quartus II software.

 

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