Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V E

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: Cyclone V GX FPGA Development Kit

How should I place the QDRII/QDRII+ mem_cq and mem_cq_n pins in Arria V GX/GT/ST/SX devices?

Description

From the device pinout file, there is only one pin location available for both mem_cq and mem_cq_n pins. For these Arria V devices complementary strobes are not supported, so only one of the mem_cq or mem_cq_n pins will be used depending on the read latency setting.

 

Workaround/Fix