Article ID: 000084514 Content Type: Troubleshooting Last Reviewed: 04/10/2023

What timing constraints should I apply for the clock signal generated from the MAX®10 internal oscillator?

Environment

  • Quartus® II Software
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Depending on your configuration of the Max® internal oscillator, you should apply one of the two timing constraints below:

    For a Clock Frequency setting of 116MHz:

    create_clock -name test -period 116MHz [get_pins -compatibility {<path to instancve>|int_osc_0|oscillator_dut|clkout}]

    For a Clock Frequency setting of 55MHz:

    create_clock -name test -period 55MHz [get_pins -compatibility {<path to instancve>|int_osc_0|oscillator_dut|clkout}]

    Resolution

    This constraint will be automatically added in a future release of the Quartus® II software.

    This problem was fixed in Intel® Quartus® software version 15.0

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs