You may see the above error when simulating your DDR3 UniPHY controller with ModelSim. The cause of the error is the ordering of the compilation libraries in the ModelSim vsim elaboration call. You must make sure the library containing the DDR3 compiled files is listed first in the command. In this case, the work directory contains the DDR3 compiled files:
vsim -novopt -t ps -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L altera_mf -L altera_lnsim -L stratixiv <top_level_filename>
It is recommended that you follow the file and library ordering in the msim_setup.tcl file provided in the <IP_variation_name>_sim/mentor directory.