Device Family: Arria® II GZ, Arria® V GX, Cyclone® V GX, Stratix® III, Stratix® IV GX, Stratix® V GX

Type: Answers

Area: Component, EMIF


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

How do I calculate the address range supported by UniPHY DDR2 or DDR3 External Memory Interface IP ?

Description

In the UniPHY DDR2 or DDR3 IP megawizard GUI -> Memory  Parameters panel, the configurable address parameters [min, max] are :- 

Row address - [12, 16]

Column address - [8, 12]

Bank address - [2, 3]

Chip select - [1, 4]     (for an unbuffered DIMM/SO-DIMM this is also number of ranks.)

If you select an illegal value for any of the address parameters, it is shown in red and you will not be able to generate the IP.

The number of addressable locations is 2^<row address> * 2^<column address>* 2^<bank_address> * <number of ranks>

The maximum number of addressable locations is currently  2^16 * 2^12* 2^3 * 4 = 8G

Multiply the number of address locations by the number of bytes in the interface data width to get the total number of G Bytes. E.g. if you have an interface width of 16 bits (2 bytes), the maximum addressable space is 8G * 2 = 16G Bytes.