Article ID: 000077059 Content Type: Product Information & Documentation Last Reviewed: 01/20/2014

How do I fully remove Common Clock Path Pessimism for my edge aligned Source-Synchronous Output Interface?

Environment

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Description

Due to a problem in the Quartus® II software version 13.1 and earlier, the TimeQuest™ Timing Analyzer removes an insufficient amount of Common Clock Path Pessmism (CCPP) for edge aligned Source-Synchronous Output Interfaces.

For cases where the clock source comes directly from an input pin then no CCPP is removed.
For cases where the clock source comes from a PLL then no CCPP is removed for the clock path between the PLL output and it's destinations.

 

Resolution

To work around this problem, manually account for any CCPP which is not automatically removed by the TimeQuest Timing Analyzer by following these steps:

1)  Run the report_timing command for each output path and include the -show_routing option
2) Calculate the total CCPP by comparing the difference between the common elements of the clock path from the "data arrival path" and "data required path" sections of the timing report
3) Manually factor this value into your timing analysis results

The total CCPP figure should then be manually factored in to your timing analysis results.

If the TimeQuest Timing Analyzer is already accounting for an amount of clock pessimism this should be subtracted from the total amount calculated from the steps above.

This problem is scheduled to be fixed for future device families.

Related Products

This article applies to 1 products

Intel® Programmable Devices