Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V E

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Device Family: Stratix® III

Device Family: Stratix® IV E

Device Family: Stratix® IV GT

Device Family: Stratix® IV GX

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: RLDRAM II Controller with UniPHY

Why does the example design for the UniPHY-based memory controller have an Avalon-MM slave port as top-level I/O?

Description

UniPHY-based memory controllers with the On-chip Debug Toolkit enabled will have an Avalon®-MM slave port exported to the top level of the example design. The additional pins required by the Avalon-MM slave port could lead to "No Fit" errors for some smaller package sizes.

Workaround/Fix

To remove the Avalon-MM slave port, you can disable the On-chip Debug Toolkit and regenerate the example design or you can manually remove the Avalon-MM slave port from the top level.

This issue will be fixed in a future release of the Quartus® II software.