Device Family: Stratix® V, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Warning : Input frequency violation on DLL instance

Description

When running simulations with Modelsim® on the UniPHY DDR3 IP with either the example testbench or the <IP _name>_sim fileset,  the simulation may generate transcript messages of type :

Note : Input frequency on DLL instance <IP_name>_example_sim.e0.if0.dll0.dll_wys_m.inst now matches with specified clock frequency.

Warning : Input frequency violation on DLL instance <IP_name>_example_sim.e0.if0.dll0.dll_wys_m.inst. Specified input period is 2500 ps but actual is 3750 ps

and the simulation never completes calibration.

 This may occur with some combinations of DDR3 UniPHY megawizard GUI -> PHY Settings parameters for "Memory clock Frequency" and "PLL reference clock frequency".

It is due to a rounding issue in the UniPHY DDR3 IP testbench clock source code

Workaround/Fix

The workaround for the example design testbench is as follows :

Verilog :

1)    In the file <IP_name>_example_sim.v,  for the pll_ref_clk instance of altera_avalon_clock_source, on code line  

.CLOCK_RATE (x)          where x is a frequency value

change x to be the frequency specified as the DDR3 megawizard PHY Settings ->  “PLL reference clock frequency”

 

VHDL :

1)  In the file submodules/altera_avalon_clock_source.vhd, change the line:

"generic (CLOCK_RATE    : integer :=10);  -- default rate 10 MHz (100ns)"

to:

"generic (CLOCK_RATE    : real :=10.0);  -- default rate 10 MHz (100ns)"



2) In the file <IP_name>_example.vhd, change

    component altera_avalon_clock_source is
        generic (
            CLOCK_RATE : positive := 10
        );
        port (
            clk : out std_logic  -- clk
        );
    end component altera_avalon_clock_source;

to:

  component altera_avalon_clock_source is
        generic (
            CLOCK_RATE : real := 10.0
        );
        port (
            clk : out std_logic  -- clk
        );
    end component altera_avalon_clock_source;



3)    In the file <IP_name>_example.vhd, change the input frequency x to the value specified in the DDR3 megawizard PHY Settings ->  “PLL reference clock frequency”.   E.g. If the input frequency is 100MHz, put 100 for the value of x.

Change

pll_ref_clk : component altera_avalon_clock_source
        generic map (
            CLOCK_RATE => x
        )
        port map (
            clk => pll_ref_clk_clk_clk  -- clk.clk
        );

to:

    pll_ref_clk : component altera_avalon_clock_source
        generic map (
            CLOCK_RATE => “PLL reference clock frequency”
        )
        port map (
            clk => pll_ref_clk_clk_clk  -- clk.clk
        );

This issue will be fixed in a future revision of the Quartus® II software.