Article ID: 000075504 Content Type: Troubleshooting Last Reviewed: 09/02/2014

Are there any known issues with pipe_pclk being inactive if txclkout is not routed through a global clock network when using Gen3 soft PIPE in Quartus II software version 12.1 on Stratix V GX devices?

Environment

  • Quartus® II Subscription Edition
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    Description Yes, there is a known issue with Gen3 soft PIPE in Quartus® II software version 12.1 on Stratix® V GX devices. If txclkout is not routed through a global clock network, pipe_pclk will be inactive.
    Resolution

    To workaround this problem you should force txclkout to use a global clock with the following QSF assignment:

    set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to
    "*sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_tx_pld_pcs_interface_rbc:inst_sv_hssi_tx_pld_pcs_interface|pld8gtxclkout"
     
    This issue will be fixed in a future version of the Quartus II software.

    Related Products

    This article applies to 3 products

    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V FPGAs

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