Device Family: Intel® Arria® 10, Arria® II, Arria® V, Cyclone® III, Cyclone® IV, Cyclone® V, Intel® MAX® 10, MAX® II, MAX® V, Stratix® III, Stratix® IV, Stratix® V

Type: Answers

Area: Component

When does the Parallel Flash Loader (PFL) IP assert the flash_nreset signal?


The flash_nreset signal will be asserted in any of the following cases:

(1) The device with the PFL design is powered up or configured.
(2) The pfl_nreset input signal is asserted.
(3) When Quartus® II programmer is used to program the flash memory, if the PFL has programming mode enabled.

If you want to assert flash_nreset, reset the PFL using pfl_nreset.