Device Family: Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: QDRII+ SRAM Controller with UniPHY

Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command

Description

Information messages regarding clock uncertainty may be seen in some UniPHY IP applications.

Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command
    Info (332172): Setup clock transfer from mem_cq_n[0] (Rise) to if0|pll0|pll_afi_clk (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.090

The reason for these messages is that in this particular case, the clock uncertainties are intentionally zero-ed out because they are already included elsewhere in the timing analyis. 

Workaround/Fix

It is recommended to search for the affected clock in the UniPHY IP SDC file and verify that statements are observed of the type :

# Clock Uncertainty is accounted for by the ...pathjitter parameters

  set_clock_uncertainty -from [ get_clocks ] 0
  set_clock_uncertainty -to [ get_clocks ] 0  

These Info messages can be safely ignored.