Article ID: 000083938 Content Type: Troubleshooting Last Reviewed: 04/04/2023

Why does my Intel® Arria® 10 fPLL output an incorrect clock frequency or misaligned clocks?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in Quartus® II version 15.0, an Intel® Arria® 10 fPLL may output incorrect clock frequencies or misaligned clocks in these circumstances:

    Case 1: The output clock frequency may be incorrect after dynamic reconfiguration between integer and fractional modes.

    Case 2: If the fPLL in core mode has multiple outputs, the output clocks may not be in phase.

     

     

    Resolution

    This problem is fixed in Intel® Quartus® Prime Software version 15.1.2 and later.

    Related Products

    This article applies to 4 products

    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 GX FPGA
    Intel® Arria® 10 SX SoC FPGA
    Intel® Arria® 10 FPGAs and SoC FPGAs

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.