Device Family: Arria® V GT, Arria® V GX, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why has the option "Enable read DQS tracking" in UniPHY based DDR3 SDRAM IP changed between Quartus II software releases?


The changes in the DDR3 Enable Read DQS Tracking option are due to the enhancement of the DDR3 IP functionality and for ease of use.

Starting with the Quartus® II software version 11.1 SP2 , the Enable Read DQS Tracking option has been removed from the UniPHY DDR3 megawizard. This option is now selected automatically when required and is determined by the FPGA device type, memory interface protocol and memory clock frequency.

It is strongly recommended that users upgrade to the latest version of the Quartus II software. However, for reference here is a summary of the Enable Read DQS Tracking parameter in earlier Quartus II software releases.

11.0SP1 : Enable Read DQS Tracking first appeared in the UniPHY DDR3 IP megawizard in the PHY Settings  ->  Advanced PHY Settings parameters.

11.1 : Enable Read DQS Tracking functionality was disabled due to a bug and is shown as greyed out in the megawizard. If your DDR3 IP has "Enable Read DQS Tracking" option selected and is greyed out, a fitter error will occur.

To turn off  Enable Read DQS Tracking, modify the UniPHY DDR3 IP top level file as shown below and regenerate the IP :

Find the line

// Retrieval info:        <generic name="DQS_TRK_ENABLED" value="true" />

and change to

// Retrieval info:        <generic name="DQS_TRK_ENABLED" value="false" />

11.1SP1 : Enable Read DQS Tracking functionality was re-enabled and is a parameter in the UniPHY DDR3 IP