Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V E

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: RLDRAM II Memory Controller

Error : Illegal constraint of DLL to the region (X, Y) to (X, Y): no valid locations in region

Description

You may experience the above fitter error when compiling a UniPHY-based memory controller in the Quartus® II version 12.1. The error occurs because there are no dedicated clock routing resources between the two PLLs.

Workaround/Fix

The workaround is to insert a clock buffer (altclkctrl) between the pll_ref_clk input and the PLLs.