An issue has been seen where the RGMII simple socket server example does not function correctly with the Cyclone® III 3c120 Development board. The reason for this is due to the timing of the RGMII interface not being compatible with the ethernet driver's configuration of the PHY.
In order to get a functional RGMII interface, a modification is required to the Altera® Avalon® TSE driver code to prevent it from changing RGMII timing control during interface initialization.
To resolve this issue, modify the following file in the Board Support Package: <bsp>/drivers/src/altera_avalon_tse.c
In the function "marvell_cfg_rgmii", comment the following line at or near line 2235 of the file:
IOWR(&pmac->mdio1.reg14, 0, dat);
//IOWR(&pmac->mdio1.reg14, 0, dat);
This will cause the ethernet PHY to work with unmodified RGMII timing control, and resolve the issue.