Device Family: Arria® II GX, Arria® II GZ, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: RLDRAM II Memory Controller

What are the minimum memory clock frequencies supported by the UniPHY External Memory Interface IP ?

Description

The minimum frequencies are defined either by the relevant JEDEC® standard or by component features of the FPGA device used to implement the External Memory Interface IP.

If too low a frequency value is entered in the UniPHY IP  PHY Settings tab -> Memory Clock Frequency, it gets displayed in red. The following error message is shown in the IP message window indicating the lowest frequency supported:

Error: The specified Memory clock frequency is below the minimum defined by the DDR specification. Please select a frequency greater than or equal to 300 MHz.

To obtain an estimate of the maximum frequency supported for any device and memory protocol configuration, use the External Memory Interface Spec Estimator tool.