IP Product: Triple Speed Ethernet MAC

Incorrect receiver clock usage in 1000Base-X with GXB Transceiver

Description

When 1000Base-X Mode is selected, incorrect receiver clock output is used by the 1000BASE-X/SGMII PCS with GXB and this will cause receiver data to have improper clock domain crossing between the transceiver and the 1000BASE-X/SGMII PCS logic. This will cause intermittent failure on the Ethernet data path, auto negotiation process, and Ethernet link synchronization.

Below is an example path to show incorrect clock domain crossing with the incorrect Latch Clock in 1000Base-X:

From Nodealtera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_gxb_gige_inst:the_altera_tse_gxb_gige_inst|altera_tse_alt4gxb_gige:the_altera_tse_alt4gxb_gige|altera_tse_alt4gxb_gige_alt4gxb_gtca:altera_tse_alt4gxb_gige_alt4gxb_gtca_component|wire_receive_pcs0_runningdisp[0]

To Nodealtera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_gxb_aligned_rxsync:the_altera_tse_gxb_aligned_rxsync|altpcs_carrierdetect

Launch Clockaltera_tse_mac_pcs_pma_gige_inst|the_altera_tse_gxb_gige_inst|the_altera_tse_alt4gxb_gige|altera_tse_alt4gxb_gige_alt4gxb_gtca_component|transmit_pcs0|clkout

Latch Clockaltera_tse_mac_pcs_pma_gige_inst|the_altera_tse_gxb_gige_inst|the_altera_tse_alt4gxb_gige|altera_tse_alt4gxb_gige_alt4gxb_gtca_component|receive_pcs0|clkout

This issue will impact the following Quartus® releases and Triple Speed Ethernet variants:

· Quartus 10.0SP1 or later

· 10/100/1000Mb Ethernet MAC with 1000Base-X/SGMII PCS

o Use transceiver block option = GXB

o Enable SGMII bridge option = Un-tick

· 1000Base-X/SGMII PCS Only

o Use transceiver block option = GXB

o Enable SGMII bridge option = Un-tick

Workaround/Fix

This issue will be fixed in Quartus 12.0.

You can follow the instructions below to apply the workaround manually:

For all IV Series Device and below:

1.       Go to triple_speed_ethernet-library folder that generated by the Triple Speed Ethernet MegaWizard™

2.       Open the “altera_tse_gxb_gige_inst.v” in any text editor

3.       Search for “ENABLE_SGMII == 0”

4.       Change the following connection under all the instance with the “ENABLE_SGMII == 0”

a.       Replace the following line:

.rx_clkout (rx_clkout),

 

To

 

.rx_clkout (),

 

b.      Add the following line under the instance:

Assign rx_clkout = tx_clkout;

5.       Repeat step 3 until all the transceiver instances with “ENABLE_SGMII == 0” are changed

6.       Recompile the design with the modify TSE library

 

For all V Series Device:

1.       Go to triple_speed_ethernet-library folder that generated by the Triple Speed Ethernet MegaWizard

2.       Open the “altera_tse_gxb_gige_phyip_inst.v” in any text editor

3.       Follow the step 3 to step 6 as IV Series device above

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