Device Family: Arria® V, Cyclone® V

Type: Answers

Area: EMIF, Intellectual Property

IP: memory-interfaces-with-uniphy

Critical Warning Mentioning Clock Transfers May Occur During Fitter Phase


This problem affects DDR2, DDR3, and QDR II products.

For half-rate soft interfaces on Arria V and Cyclone V devices, the following warning might appear during the fitter phase:

Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.

The above warning applies to hold time uncertainty between the AFI clock domain and the address and command clock domain. You may ignore this warning.


The workaround for this issue is to ignore the displayed warning. Alternatively, you can suppress the warning, as described below.

Open the generated <instance_name>_if0_p0.sdc file in an editor and locate the Fitter Overconstraints section of the file.

Add the following lines to the Fitter Overconstraints section of the file:

if {} { # Suppress clock uncertainty warning for hold-time: set_clock_uncertainty -from [get_clocks ] -to [get_clocks ] -add -hold 0.000 }

Save the changes to the file.