Type: Answers, Errata

Area: EMIF, Intellectual Property



Error When Simulating DDR3 with Ping Pong PHY Using VHDL and ModelSim

Description

This problem affects DDR3 products.

A simulation error can occur when you simulate a quarter-rate DDR3 design using VHDL and ModelSim, with Ping Pong PHY enabled and the calibration mode set to Quick or Full.

Workaround/Fix

The workaround for this issue is to do one of the following: set the calibration mode to Skip; use Verilog instead of VHDL; or use a different simulator.

This issue will be fixed in a future release.