Type: Answers, Errata

Area: EMIF, Intellectual Property

Inconsistent Ordering of Local Memory Addresses in Example Design


This problem affects ALTMEMPHY-based DDR, DDR2 and DDR3 products.

The memory controller follows a default local-memory addressing order of chip-row-bank-column, whereas the example driver follows an ordering of chip-bank-row-column. The memory bus may display inconsistent memory address transactions because the ordering of the controller differs from the ordering of the example driver.


The workaround for this issue is to choose a local memory address ordering of chip-bank-row-column in the Controller GUI.

This issue will not be fixed.