Type: Answers, Errata

Area: EMIF, Intellectual Property



Board Skew Analysis Is Incorrect for Arria V and Cyclone V Devices

Description

This problem affects DDR2 and DDR3 products.

Board skew analysis of the DQS to CK timing relationship is performed as part of the Report DDR command. The calculation for the setup and hold margin of the DQS to CK relationship is incorrect.

Workaround/Fix

The workaround for this issue is to generate your external memory interface, and then make the following changes to the interface_name<>_if0_p0.sdc file in the UniPHY IP submodules folder:

  1. Find the DQS vs CK timing constraints in the .sdc file. This is the set_output_delay constraints in the DQS vs CK PATH section of the file.
  2. Modify the term in the -max and -min constraints from being added to being subtracted.
  3. Swap (minCK_DQS_skew) for (maxCK_DQS_skew) in the constraints.
  4. The correct constraints are as follows:

    set_output_delay -add_delay -clock [get_clocks ]� -max [{interface_name}_round_3dp [expr (CK) - (DQSS)� *(CK) - (minCK_DQS_skew) ]] � set_output_delay -add_delay -clock [get_clocks ]� -min [{interface_name}_round_3dp [expr (DQSS)*(CK)� -(maxCK_DQS_skew) ]] �

    After you implement this workaround, the TimeQuest will analyze the DQS to CK relationship correctly. You might not see a change in the reported setup and hold margin, if your minCK_DQS_skew is the negative of the maxCK_DQS_skew.

This issue will be fixed in a future version.