Type: Answers

Type: Errata

Area: EMIF

Area: Intellectual Property



ECC Logic Always Enabled in Controller when CSR is Enabled

Description

This problem affects DDR2, DDR3, and LPDDR2 products.

When the controller setting Enable Configuration and Status Register Interface is enabled and Enable Error Detection and Correction Logic is not enabled, the ECC soft logic is nonetheless enabled in the IP core. This results in additional resource usage and can decrease the controller’s possible fmax.

Workaround/Fix

The workaround for this issue is to as follows:

  1. In a text editor, open the file alt_mem_ddrx_csr.v.
  2. Near the top of alt_mem_ddrx_csr.v, change CTL_ECC_CSR_ENABLED = 1 to CTL_ECC_CSR_ENABLED = 0.
  3. In alt_mem_ddrx_csr.v, locate the following block of code:
  4. if (!CTL_ECC_CSR_ENABLED) begin assign cfg_enable_ecc = 1\'b1; // default value assign cfg_enable_auto_corr = 1\'b1; // default value assign cfg_gen_sbe = 0; assign cfg_gen_dbe = 0; assign cfg_enable_intr = 1\'b1; // default value assign cfg_mask_sbe_intr = 0; assign cfg_mask_dbe_intr = 0; assign cfg_clr_intr = 0; assign cfg_mask_corr_dropped_intr=0; end

    Change the block of code to the following:

    if (!CTL_ECC_CSR_ENABLED) begin assign cfg_enable_ecc = 1\'b0; // default value assign cfg_enable_auto_corr = 1\'b0; // default value assign cfg_gen_sbe = 0; assign cfg_gen_dbe = 0; assign cfg_enable_intr = 1\'b0; // default value assign cfg_mask_sbe_intr = 0; assign cfg_mask_dbe_intr = 0; assign cfg_clr_intr = 0; assign cfg_mask_corr_dropped_intr=0; end �

This issue will be fixed in a future version.