Type: Answers

Type: Errata

Area: EMIF

Last Modified: November 18, 2016
Version Found: v16.0
Version Fixed: v16.1
Bug ID: FB369334;

Internal Error: Sub-system: ASMIO, File: /quartus/comp/asmio/asmio_reg.cpp, Line: 6596


If you apply the set_max_skew Synopsys Design Constraints (SDC) constraint to a DQSn pin in a MAX® 10 design that includes the LPDDR2 EMIF IP, the Quartus® Prime Standard Edition software\'s Assembler encounters an internal error.

This issue affects MAX 10 designs that target the 10M16, 10M25, or 10M50 devices.