QDR II interfaces on Arria 10 devices may experience difficulty achieving timing closure. This problem is most evident when core-to-periphery and periphery-to-core transfers approach 333 MHz, with PLL VCO of less than 600 MHz.
Device Family: Intel® Arria® 10
Type: Answers, Errata
Area: EMIF, Intellectual Property
The workaround for this problem is to do one of the following:
- Try compiling with multiple seeds.
- Use a PLL VCO value of greater than 600 MHz.