Device Family: Intel® Arria® 10

Type: Answers

Type: Errata

Area: EMIF

Area: Intellectual Property



New Restrictions on I/O PLL Configuration Imposed in 15.1 for Arria 10 EMIF IP

Description

In version 15.1, the valid range of selectable PLL Reference Clock Frequency values is reduced.

  • For VCO frequencies below 400 MHz, the value of the PLL M counter must now be within the range of 2 to 7, inclusive.
  • For VCO frequencies between 400 MHz and 600 MHz, the value of the PLL M counter must be within the range of 2 to 15, inclusive.
  • For VCO frequencies equal to or greater than 600 MHz, the value of the PLL M counter must be greater than or equal to 4.

Users with designs parameterized on an earlier version may encounter errors when generating their EMIF IP in version 15.1.

Workaround/Fix

There is no workaround for this issue.

This issue will not be fixed.