rx_align_clr signal resets the RX FIFO buffer, and the signal has both a synchronous path to the read clock domain, and an asynchronous path to the write clock domain of the FIFO buffer.
For the Stratix V, Arria V GZ, and Arria 10 devices, the retiming engine does not recognize the asynchronous path to the write clock domain and resets and improves the logic timing. This can result in an unregistered combinatorial signal directly connected to the synchronizer in the write clock domain, which causes the RX FIFO buffer to clear, causing data disparity.
This issue can occur when the register retiming compilation option is enabled for the following interfaces:
- Transceiver Native PHY (with 10 G PCS enabled and RX_FIFO mode set to Interlaken)
- 50 G Interlaken
- 100 G Interlaken
- Interlaken PHY
- SerialLite III Streaming