The Low Latency 40-100GbE IP core IPG_COL_REM register at offset 0x406 should have the value of 20 decimal in 100GbE variations and the value of 4 decimal in 40GbE variations. However, the LL 40-100GbE IP core v14.1 sets this register to the value of 4 in 100GbE variations.
This issue applies to all LL 100GbE IP cores for which you specify an inter-packet gap in the LL 40-100GbE parameter editor.
This issue reduces the bandwidth of the LL 100GbE IP core.