Type: Answers

Type: Errata

Area: Intellectual Property



Some Low Latency 40-100GbE IP Core Status Registers Are Not Readable

Description

The following LL 40-100GbE IP core TX statistics and RX statistics status registers are not correctly readable in the IP core v14.1:

  • TXSTAT_REVID at offset 0x840
  • TXSTAT_SCRATCH at offset 0x841
  • TXSTAT_NAME_0, TXSTAT_NAME_1, and TXSTAT_NAME_2 at offsets 0x842-0x844
  • CNTR_TX_CONFIG at offset 0x845
  • CNTR_TX_STATUS at offset 0x846
  • RXSTAT_REVID at offset 0x940
  • RXSTAT_SCRATCH at offset 0x941
  • RXSTAT_NAME_0, RXSTAT_NAME_1, and RXSTAT_NAME_2 at offsets 0x942-0x944
  • CNTR_RX_CONFIG at offset 0x945
  • CNTR_RX_STATUS at offset 0x946

Workaround/Fix

This issue has no workaround. Do not rely on the values you read from these registers.

This issue is fixed in version 15.1 of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP core.