The Altera-provided testbench generated with the Low Latency 40-100GbE IP core CAUI-4 variations cannot simulate successfully in the ModelSim simulator.
Area: Intellectual Property
This issue has no general workaround tested for all affected IP core versions. However, the following workaround is available for version 15.0 of the IP core:
- Generate the testbench for your CAUI-4 IP core variation. Instructions are available in the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide.
- Open the run_vsim.do script in the location specified in the user guide. The script includes a statement that identifies the path to the msim_setup.tcl file.
- Open the msim_setup.tcl file in a text editor.
- In the
elab_debugtasks, replace the text
eval vsim -t pswith the text
eval vsim -t 100fs.
- Run the testbench according to the instructions in the user guide. The testbench should simulate successfully.
This issue will be fixed in a future version of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore function.