Low Latency 40-100GbE IP Core Targeting Stratix V Device With 322 MHz Reference Clock Has Wrong RX MAC Clock Frequency

The LL 40-100GbE parameter editor provides two possible values for the PHY reference frequency parameter. Both values should generate a clk_rxmac frequency of 312.5 MHz for 40GbE variations and 390.625 MHz for 100GbE variations.

However, in IP core variations with the following properties, the clk_rxmac frequency is different:

• The target device family is the Stratix V device family.
• The PHY reference frequency parameter has the value of 322.265625 MHz.