Critical Issue
Description
When you compile the Low Latency 40-100GbE IP core released with the Quartus II software v14.0 Arria 10 Edition, you might encounter the following timing issues:
- CAUI-4 LL 40-100GbE IP core variations might flag pulse width violations
- LL 100GbE IP core variations might have setup violations
- All LL 40-100GbE IP core variations might have hold violations
Resolution
This issue has no workaround.
This issue will be fixed in a future version of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore function.