For the Arria V, Cyclone V, and Stratix V devices, you can
use the Altera phase-locked loop (PLL) reconfiguration IP to dynamically
reconfigure the settings of the device fractional PLL (fPLL). Asserting
mgmt_reset signal on the PLL reconfiguration IP restores
the fPLL to its original SRAM Object File (.sof) settings.
This restore function is for V-series devices only; it does not
exist when reconfiguring the I/O PLL or fPLL in the Arria 10 device.
You can use the PLL reconfiguration IP to reconfigure the
I/O PLLs settings, but asserting the
on the IP will not restore the original .sof settings
of the I/O PLL. Asserting the
reset signal clears the
command FIFO buffer in the IP. If you assert the I/O PLL reset,
the I/O PLL will lose and regain lock, but the new settings will
For the Arria 10 device, the high-speed serial interface (HSSI) fPLL has an Avalon Memory-Mapped (Avalon-MM) interface for reconfiguration. The Avalon-MM interface is raw to allow you to dynamically change settings at run time. Your new fPLL settings are preserved when asserting the transceiver dynamic reconfiguration reset, the PLL reset, or both resets.