Low Latency 40-100GbE IP Core Implements Avalon-MM Specification Incorrectly on Control and Status Interface

The Low Latency 40-100GbE IP core control and status interface provides access to the IP core registers and is supposed to implement the Avalon-MM interface slave protocol. However, the IP core does not implement this protocol correctly. Specifically, the status_waitrequest output signal does not comply with the specification. The IP core does not deassert this signal until after the application deasserts the status_read or status_write input signal.

According to the Avalon-MM protocol specification, the master (the application) must hold the read or write request signal asserted until the slave deasserts the waitrequest signal. However, with the current IP core implementation, the IP core will erroneously assume multiple requests if the master asserts the read or write request signal when the busy signal is asserted.

For more information about the Avalon-MM specification, refer to Avalon Interface Specifications.

To work around this issue, the application should issue a new read or write request (assert status_read or status_write) only when the status_waitrequest signal is de-asserted, and must hold the status_read or status_write signal high for only a single clock cycle.

This issue is fixed in version 14.0 of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore function.