The Low Latency 40-100GbE IP core control and status interface
provides access to the IP core registers and is supposed to implement
the Avalon-MM interface slave protocol. However, the IP core does
not implement this protocol correctly. Specifically, the
signal does not comply with the specification. The IP core does
not deassert this signal until after the application deasserts the
According to the Avalon-MM protocol specification, the master (the application) must hold the read or write request signal asserted until the slave deasserts the waitrequest signal. However, with the current IP core implementation, the IP core will erroneously assume multiple requests if the master asserts the read or write request signal when the busy signal is asserted.
For more information about the Avalon-MM specification, refer to Avalon Interface Specifications.