Device Family: Intel® Arria® 10

Type: Answers, Errata

Area: EMIF, Tools

Internal Error in Chip Planner/LogicLock during EMIF/PHYLite Compilation


If you use the Quartus II software Arria 10 Edition v13.1 to compile a design containing an external memory interface (EMIF) or PHYLite interface, the following error message might appear:

Internal Error: Sub-system: CPLL, File: /quartus/periph/cpll/refclk_gen6_param_util.cpp, Line: 113

start: 1, end: 2, driver: 4


Place the reference clock pin and one EMIF or PHYLite I/O pin in the same IO_BANK.