Device Family: Arria® V, Cyclone® V

Type: Answers, Errata

Area: EMIF, Intellectual Property, Tools



Long Term CK Jitter Exceeds Spec in HPS Memory Interface in Arria V and Cyclone V Devices

Description

This problem affects DDR2, DDR3, and LPDDR2 products.

DDR2, DDR3, and LPDDR2 interfaces using the HPS memory interface on Arria V or Cyclone V devices, produce a long term CK jitter (on the HPS side, not the FPGA side) that exceeds the JEDEC and vendor specification (tERR(Nper) for moderate values of N).

Workaround/Fix

Altera has verified that adherence to this spec is not required, provided that short-term jitter (tJITcc and tJITper) requirements are met. In the configurations described, tJITcc and tJITper are within the JEDEC specifications.

This issue will not be fixed.