Device Family: Arria® V, Cyclone® V

Type: Answers, Errata

Area: EMIF, Intellectual Property, Tools



Possible Timing Failure on Designs Targeting Arria V and Cyclone V Devices

Description

This problem affects DDR2, DDR3, and LPDDR2 SDRAM Controllers with UniPHY.

DDR2, DDR3, and LPDDR2 soft interfaces on Arria V GX/GT/SoC or Cyclone V and SoC devices may experience problems achieving timing closure at certain maximum frequencies.

Specifically, this problem affects soft interfaces with the following configurations:

  • Arria V quarter-rate DDR3 at 600 MHz or above
  • Arria V half-rate LPDDR2 at 300 MHz or above
  • Cyclone V half-rate DDR3 at 300 MHz
  • Cyclone V half-rate DDR2 at 300 MHz

Workaround/Fix

The workaround for this issue is to apply the appropriate solution for your configuration, as described below.

DDR3, DDR3L and LPDDR2 SDRAM EMIF Specification Update for Arria V GX/GT/SoC Devices

  • For Arria V GX/GT/SoC, -I3 speed grade device interfacing with a DDR3 SDRAM component with 1 chip selects using soft memory controller at 667 MHz: Upgrade the DDR3 SDRAM component to a 1066 MHz DDR3 SDRAM component to achieve the specified maximum frequency.
  • For Arria V GX/GT/SoC, -I3 speed grade device interfacing with a DDR3L SDRAM component with 1 chip selects using soft memory controller: The maximum frequency is downgraded to 600MHz.
  • For Arria V GX/GT/SoC, -C4 speed grade device interfacing with a DDR3 SDRAM component with 1 chip selects using soft memory controller: The maximum frequency is downgraded to 600 MHz for design with Total Interface Width of 64 bits and above and 633 MHz for design with Total Interface Width below 64 bits. Upgrade the DDR3 SDRAM component to a 1066 MHz DDR3 SDRAM component to achieve the specified maximum frequency.
  • For Arria V GX/GT/SoC, -C4 speed grade device interfacing with a DDR3L SDRAM component with 1 chip selects using soft memory controller: The maximum frequency is downgraded to 600 MHz.
  • For Arria V GX/GT/SoC, -C5 speed grade device interfacing with a DDR3L SDRAM component with 1 chip selects using soft memory controller at 533 MHz: Upgrade the DDR3L SDRAM component to a 800 MHz DDR3 SDRAM component to achieve the specified maximum frequency.
  • For Arria V GX/GT/SoC, -C5 and I5 speed grade device interfacing with a LPDDR2 SDRAM component with 1 chip selects using soft memory controller at 333 MHz: Upgrade the LPDDR2 SDRAM component to a 400 MHz DDR3 SDRAM component to achieve the specified maximum frequency.
  • For Arria V GX/GT/SoC, -C6 speed grade device interfacing with a LPDDR2 SDRAM component with 1 chip selects using soft memory controller at 300 MHz: Upgrade the LPDDR2 SDRAM component to a 400 MHz DDR3 SDRAM component to achieve the specified maximum frequency.

For other affected configurations that are not covered by this spec update, if you experience timing failure, compile the IP using multiple seeds and additional synthesis and fitter optimizations enabled.

This issue will not be fixed.

The solutions for maximum frequency specifications have been updated in the External Memory Interface Spec Estimator.