Article ID: 000076055 Content Type: Troubleshooting Last Reviewed: 02/05/2014

Cadence NCSim VHDL Compilation Error for Low Latency Ethernet 10G MAC

Environment

  • Quartus® II Subscription Edition
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The Cadence NCSim VHDL simulator may cause compilation error for Low Latency Ethernet 10G MAC designs. The simulator library mapping in the Qsys .spd file shows the following error or similar:

    ncelab: *W,ARCMRA: Elaborating the WORK.TOP_TB:RTL, MRA (most recently analyzed) architecture.ncelab: *E,MULVLG: Possible bindings for instance of design unit 'altera_reset_controller' in 'top_inst.top_tb_top_inst:rtl' are: alt_em10g32_0.altera_reset_controller:module rst_controller.altera_reset_controller:module.ncelab: *W,CUNOTB: component instance is not fully bound (:top_tb:top_inst:rst_controller) [File:top_tb_top_inst.vhd, Line:352].ncsim: 12.20-s014: (c) Copyright 1995-2013 Cadence Design Systems, Inc.ncsim: *F,NOSNAP: Snapshot 'top_tb' does not exist in the libraries

    Resolution

    To work around this issue, regenerate the simulation scripts using the following command:

    ip-make-simscript --spd=<spd_file> --compile-to-work

    This issue will be fixed in a future version of the Quartus II software.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices