This problem affects DDR2 and DDR3 interfaces on Arria V and Cyclone V devices.
In version 14.0, a change was made to the ArriaV and Cyclone
V hard memory controller (for both HPS and non-HPS configurations)
that enables the I/O output buffer termination approximately one
memory clock cycle earlier than the output buffer enable. This change
was made to improve the write preamble duration (
DDR2 and DDR3 interfaces. However, this change also causes an increase
in static power dissipation, because it enables read OCT termination
when the interface is idle.
This change is reverted in version 14.1.
If you are using version 14.0 or 14.1, and encounter functional
failures directly attributable to
tWPRE timing, contact
Altera Technical Services for a workaround.