Device Family: Arria® V

Type: Answers, Errata

Area: EMIF, Intellectual Property



LPDDR2 Interfaces on Arria V SoC Devices May Fail Postamble Timing

Description

This problem affects LPDDR2 products.

Due to preliminary timing models, LPDDR2 interfaces on Arria V SoC devices may fail Postamble Timing in Report DDR.

Workaround/Fix

The workaround for this issue is to ignore the postamble timing failures.

This issue will be fixed in a future version.